(a) Field of the Invention
The present invention relates to a flash memory device and a method of manufacturing the same.
(b) Description of the Related Art
Generally, a flash memory is devised to combine advantages of both EPROM (erasable programmable read only memory) and EEPROM (electrically erasable PROM), which provides a device enabling electrical data programming and erasing with a low manufacturing cost due to a simple manufacturing process and small chip size. Such a flash memory device is composed of a floating gate, a control gate, and a silicon substrate including an isolation layer, a tunnel oxide, and an insulation layer. In addition, program and erase operations are electrically performed.
Such a flash memory device includes a common source line for connecting a source of each cell. Such a common source is formed by performing an ion-implantation through a SAS (Self Aligned Source) process.
More particularly, the SAS process is performed by the following procedures. Firstly, a gate electrode is formed in a stacking structure including a field oxide layer and an isolation layer, and then a source region of a cell is opened by using an additional SAS mask. Subsequently, the field oxide layer and the isolation layer are removed by an anisotropic etching process so as to form a common source line.
Since a common source line in a flash memory cell using such a SAS process may be formed along a profile of a trench, and contact resistance of a source per cell may be significantly increased. The reason for the significant increase of resistance of the common source line is that since junction resistance is formed along a surface of a trench region, the actual surface resistance extends along the trench profile and the resistivity of the sidewall in the trench increases. That is, in performing the ion-implantation, since a relatively small amount of impurity is ion-implanted on sidewalls of the trench region, resistance of the common source line is significantly increased.
In addition, if an isolation layer is not completely removed, resistance of the common source line may be significantly increased because impurities may be non-uniformly implanted into the trench region.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.